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an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. tps54824 slvsdc9 ? november 2016 tps54824 4.5-v to 17-v input, current mode, 8-a synchronous swift ? step-down converter 1 1 features 1 ? small 3.5-mm x 3.5-mm hotrod ? qfn package ? integrated 14.1-m ? and 6.1-m ? mosfets ? peak current mode control with fast transient response ? 200-khz to 1.6-mhz fixed switching frequency ? synchronizes to external clock ? 0.6-v voltage reference 0.85% over temperature ? 0.6-v to 12-v output voltage range ? hiccup current limit ? safe startup into pre-biased output voltage ? adjustable soft-start and power sequencing ? adjustable input under voltage lockout ? 3- a shutdown current ? power good output monitor for undervoltage and overvoltage ? output overvoltage protection ? non-latch thermal shutdown protection ? ? 40 c to 150 c operating junction temperature ? supported at the webench ? design center 2 applications ? telecom and wireless infrastructure ? industrial automated test equipment ? enterprise switching and storage applications ? high density distributed power systems 3 description the tps54824 is a full featured 17-v, 8-a synchronous step-down converter in a 3.5 mm x 3.5 mm hotrod ? qfn package. the device is optimized for small solution size through high efficiency and integrating the high-side and low-side mosfets. further space savings are achieved through peak current mode control, which reduces component count, and by selecting a high switching frequency, reducing the inductor footprint. the peak current mode control simplifies the loop compensation and provides fast transient response. cycle-by-cycle peak current limiting on the high-side and low-side sourcing current limit protects the device in overload situations. hiccup limits mosfet power dissipation if a short circuit or over loading fault persists. a power good supervisor circuit monitors the regulator output. the pgood pin is an open drain output and goes high impedance when the output voltage is in regulation. an internal deglitch time prevents the pgood pin from pulling low unless a fault has occurred. a dedicated en pin can be used to control the regulator on/off and adjust the input under voltage lockout. the output voltage startup ramp is controlled by the ss/trk pin which allows operation as either a standalone power supply or in tracking situations. device information (1) part number package body size (nom) tps54824 rnv (18) 3.50 mm x 3.50 mm (1) for all available packages, see the orderable addendum at the end of the data sheet. simplified schematic efficiency output current (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 50 55 60 65 70 75 80 85 90 95 100 d001 12 v to 3.3 v, 800 khz, l = 1 h, dcr = 8.4 m : 12 v to 1.5 v, 600 khz, l = 1 h, dcr = 8.4 m : 9 v to 1 v, 700 khz, l = 680 nh, dcr = 7 m : 5 v to 1 v, 700 khz, l = 680 nh, dcr = 7 m : vin en pgood ss/trk rt/clk comp boot sw fb agnd pgnd c bt l o c o r fbt r fbb c ss r t c p c z r c c i v in v out copyright ? 2016, texas instruments incorporated tps54824 productfolder sample &buy technical documents tools & software support &community
2 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 switching characteristics .......................................... 6 6.7 timing requirements ................................................ 6 6.8 typical characteristics .............................................. 6 7 detailed description ............................................ 11 7.1 overview ................................................................. 11 7.2 functional block diagram ....................................... 12 7.3 feature description ................................................. 12 7.4 device functional modes ........................................ 20 8 application and implementation ........................ 21 8.1 application information ............................................ 21 8.2 typical application ................................................. 21 9 power supply recommendations ...................... 30 10 layout ................................................................... 30 10.1 layout guidelines ................................................. 30 10.2 layout example .................................................... 30 10.3 alternate layout example ..................................... 32 11 device and documentation support ................. 33 11.1 receiving notification of documentation updates 33 11.2 community resources .......................................... 33 11.3 trademarks ........................................................... 33 11.4 electrostatic discharge caution ............................ 33 11.5 glossary ................................................................ 33 12 mechanical, packaging, and orderable information ........................................................... 33 4 revision history date revision notes november 2016 * initial release.
3 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 5 pin configuration and functions rnv package 18-pin vqfn-hr top view bottom view pin functions pin i/o description name no. boot 1 i floating supply voltage for high-side mosfet gate drive circuit. connect a 0.1- f ceramic capacitor between boot and sw pins. vin 2, 11 i input voltage supply pin. power for the internal circuit and the connection to drain of high- side mosfet. connect both pins to the input power source with a low impedance connection. connect both pins and their neighboring pgnd pins. pgnd 3, 4, 5, 8, 9, 10 ? ground return for low-side power mosfet and its drivers. sw 6, 7 o switching node. connected to the source of the high-side mosfet and drain of the low-side mosfet. agnd 12 ? ground of internal analog circuitry. agnd must be connected to the pgnd plane. rt/clk 13 i switching frequency setting pin. in rt mode, an external timing resistor adjusts the switching frequency. in clk mode, the device synchronizes to an external clock input to this pin. fb 14 i converter feedback input. connect to the output voltage with a resistor divider. comp 15 i error amplifier output and input to the pwm modulator. connect loop compensation to this pin. ss/trk 16 i soft-start and tracking pin. connecting an external capacitor sets the soft-start time. this pin can also be used for tracking and sequencing. en 17 i enable pin. float or pull high to enable the device. connect a resistor divider to this pin to implement adjustable under voltage lockout and hysteresis. pgood 18 o open-drain power good indicator. it is asserted low if output voltage is outside if the pgood thresholds, vin is low, en is low, device is in thermal shutdown or device is in soft-start. 1 boot 2 vin 3 pgnd 4 pgnd 5 pgnd 6 sw vin 11 13 rt/clk 14 fb 15 comp 16 ss/trk 17 en 18 pgood agnd 12 pgnd 10 pgnd 9 pgnd 8 7 sw boot 1 vin 2 pgnd 3 pgnd 4 pgnd 5 12 agnd 11 vin 10 pgnd 9 pgnd 8 pgnd 13 rt/clk 14 fb 15 comp 16 ss/trk 17 en 18 pgood 7 sw 6 sw
4 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit voltage vin ? 0.3 18 v boot ? 0.3 25 boot (10 ns transient) ? 0.3 27 boot (vs sw) ? 0.3 6.5 sw ? 1 19 sw (10 ns transient) ? 3 21 en, ss/trk, pgood, rt/clk, fb, comp ? 0.3 6.5 operating junction temperature range, t j -40 150 c storage temperature range, t stg -55 150 c (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 6.2 esd ratings value unit v (esd) electrostatic discharge human body model (hbm), per ansi/esda/jedec js-001, all pins (1) 2000 v charged device model (cdm), per jedec specification jesd22-c101, all pins (2) 500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) parameter min nom max unit v in input voltage range 4.5 17 v v out output voltage 0.6 12 v i out output current 8 a t j operating junction temperature -40 150 c f sw switching frequency (rt mode and pll mode) 200 1600 khz (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report, spra953. 6.4 thermal information thermal metric (1) tps54824 unit rnv 18 pins theta ja junction-to-ambient thermal resistance jedec 57.1 c/w theta ja junction-to-ambient thermal resistance evm 34 c/w theta jctop junction-to-case (top) thermal resistance 26.3 c/w theta jb junction-to-board thermal resistance 18.8 c/w psi jt junction-to-top characterization parameter 0.8 c/w psi jb junction-to-board characterization parameter 18.8 c/w theta jcbot junction-to-case (bottom) thermal resistance 1.2 c/w
5 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 6.5 electrical characteristics t j = -40 c to 150 c, vin = 4.5 v to 17 v (unless otherwise noted) parameter test conditions min typ max unit input voltage uvlo_rise vin under-voltage lockout v (vin) rising 4.1 4.3 v uvlo_fall v (vin) falling 3.7 3.9 v uvlo_hys hysteresis vin voltage 0.2 v ivin operating non-switching supply current v (en) = 5 v, v (fb) = 1.5 v 580 800 a ivin_sdn shutdown supply current v (en) = 0 v 3 11 a enable ven_rise en threshold v (en) rising 1.20 1.26 v ven_fall v (en) falling 1.1 1.15 v ven_hys en pin threshold voltage hysteresis 50 mv ip en pin sourcing current v (en) = 1.1v 1.2 a iph en pin sourcing current v (en) = 1.3v 4.8 a ih en pin hysteresis current 3.6 a fb v fb regulated fb voltage t j = 25 c 596 600 604 mv 595 600 605 mv error amplifier gmea error amplifier transconductance (gm) ? 2 a < i (comp) < 2 a, v (comp) = 1 v 1100 a/v error amplifier dc gain 80 db icomp_src error amplifier source current v (fb) = 0 v 100 a icomp_snk error amplifier sink current v (fb) = 2 v -100 a gmps power stage transconductance 16 a/v soft-start iss soft-start current 5 a v (ss/trk) to v (fb) matching v (ss/trk) = 0.4 v 25 mv mosfet rds(on)_h high-side switch resistance t a = 25 c, v (vin) = 12 v 14.1 m t a = 25 c, v (vin) = 4.5 v, v (boot-sw) = 4.5 v 15.9 m rds(on)_l low-side switch resistance t a = 25 c, v (vin) = 12 v 6.1 m t a = 25 c, v (vin) = 4.5 v 6.9 m boot uvlo falling 2.2 2.6 v current limit ioc_hs_pk high-side peak current limit 10.8 12.9 15 a ioc_ls_snk low-side sinking current limit ? 3.4 a ioc_ls_src low-side sourcing current limit 9.3 11.4 13.6 a rt/clk v ih logic high input voltage 2 v v il logic low input voltage 0.8 v pgood power good threshold v (fb) rising (fault) 108% v (fb) falling (good) 106% v (fb) rising (good) 91% v (fb) falling (fault) 89% ipg_lkg leakage current when pulled high v (pgood) = 5 v 5 na vpg_low pgood voltage when pulled low i (pgood) = 2 ma 0.3 v minimum vin for valid output v (pgood) < 0.5 v, i (pgood) = 4 ma 0.7 1 v thermal protection t trip thermal protection trip point temperature rising 170 c t hyst thermal protection hysteresis 15 c
6 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated (1) specified by design. 6.6 switching characteristics t j = -40 c to 150 c, v (vin) = 4.5 v to 17 v (unless otherwise noted) parameter test conditions min typ max unit en en to start of switching 135 s pgood deglitch time pgood going high 272 cycles deglitch time pgood going low 16 cycles sw ton_min minimum on time measured at 50% to 50% of v in , l = 0.68 h, i out = 0.1 a 95 ns toff_min minimum off time (1) v (boot-sw) 2.6 v 0 ns rt/clk fsw_min minimum switching frequency (rt mode) r (rt/clk) = 250 k 200 khz switching frequency (rt mode) r (rt/clk) = 100 k 450 500 550 khz fsw_max maximum switching frequency (rt mode) r (rt/clk) = 30.1 k 1.6 mhz fsw_clk switching frequency synchronization range (pll mode) 200 1600 khz rt/clk falling edge to sw rising edge delay (pll mode) measure at 500khz with rt resistor in series with rt/clk 70 ns hiccup wait time before hiccup 512 cycles hiccup time before restart 16384 cycles 6.7 timing requirements t j = -40 c to 150 c, v (vin) = 4.5 v to 17 v (unless otherwise noted) min nom max unit rt/clk minimum synchronization signal pulse width (pll mode) 35 ns 6.8 typical characteristics figure 1. efficiency for 9 v input to 1 v output figure 2. efficiency for 12 v input to 1.5 v and 0.8 v output output current (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 50 55 60 65 70 75 80 85 90 95 100 d003 12 v to 1.5 v, 600 khz, l = 1 h, dcr = 8.4 m : 12 v to 1.5 v, 700 khz, l = 680 nh, dcr = 7 m : 12 v to 0.8 v, 400 khz, l = 680 nh, dcr = 7 m : output current (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 50 55 60 65 70 75 80 85 90 95 100 d002 9 v to 1 v, 700 khz, l = 680 nh, dcr = 7 m : 9 v to 1 v, 600 khz, l = 680 nh, dcr = 7 m :
7 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) figure 3. efficiency for 12 v input to 3.3 v output v (en) = 5 v v (fb) = 0.8 v figure 4. vin pin nonswitching supply current vs junction temperature v (en) = 0.4 v figure 5. vin pin shutdown current vs junction temperature figure 6. en pin voltage threshold vs junction temperature figure 7. en pin current vs junction temperature figure 8. regulated fb voltage vs junction temperature junction temperature ( q c) en pin output current ( p a) -50 -25 0 25 50 75 100 125 150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 d008d007 v (en) = 1.1 v v (en) = 1.3 v junction temperature ( q c) voltage reference (v) -50 -25 0 25 50 75 100 125 150 0.595 0.596 0.597 0.598 0.599 0.6 0.601 0.602 0.603 0.604 0.605 d009 junction temperature ( q c) en voltage threshold (v) -50 -25 0 25 50 75 100 125 150 1.12 1.13 1.14 1.15 1.16 1.17 1.18 1.19 1.2 1.21 1.22 d007 en rising en falling junction temperature ( q c) vin pin shutdown supply current ( p a) -50 -25 0 25 50 75 100 125 150 0 1 2 3 4 5 6 7 8 9 10 d006 v in = 4.5 v v in = 12 v v in = 17 v output current (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 50 55 60 65 70 75 80 85 90 95 100 d004 12 v to 3.3 v, 800 khz, l = 1 h, dcr = 8.4 m : 12 v to 3.3 v, 1 mhz, l = 1 h, dcr = 8.4 m : junction temperature ( q c) nonswitching supply current ( p a) -50 -25 0 25 50 75 100 125 150 500 510 520 530 540 550 560 570 580 590 600 610 620 d005 v in = 4.5 v v in = 12 v v in = 17 v
8 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) figure 9. mosfet rds(on) vs junction temperature figure 10. error amplifier transconductance vs junction temperature figure 11. comp to sw transconductance vs junction temperature figure 12. ss/trk current vs junction temperature v (ss/trk) = 0.4 v figure 13. ss/trk to fb offset vs junction temperature figure 14. fb voltage vs ss/trk voltage junction temperature ( q c) mosfet r ds(on) (m : ) -50 -25 0 25 50 75 100 125 150 2 4 6 8 10 12 14 16 18 20 22 24 26 28 d010 high-side, v (boot-sw) = 4.5 v high-side, v (vin) = 12 v low-side, v (vin) = 4.5 v low-side, v (vin) = 12 v junction temperature ( q c) error amplifier transconductance ( p s) -50 -25 0 25 50 75 100 125 150 900 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 d011 junction temperature ( q c) v (ss/trk) to v (fb) matching (mv) -50 -25 0 25 50 75 100 125 150 20 22 24 26 28 30 32 34 36 38 40 d014 v (ss/trk) (v) v (fb) (v) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 d022 junction temperature ( q c) v (comp) to i (sw) transconductance (s) -50 -25 0 25 50 75 100 125 150 12 13 14 15 16 17 18 19 d012 junction temperature ( q c) i (ss/trk) (a) -50 -25 0 25 50 75 100 125 150 4.7 4.75 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 5.25 5.3 d013
9 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) figure 15. high-side peak current limit vs junction temperature figure 16. pgood thresholds vs junction temperature v (fb) = 0.6 v v (pgood) = 5 v figure 17. pgood leakage current vs junction temperature v in = 12 v l = 0.68 h figure 18. minimum on-time vs ambient temperature r (rt/clk) = 100 k figure 19. switching frequency vs junction temperature (500 khz) r (rt/clk) = 30.1 k figure 20. switching frequency vs junction temperature (1600 khz) junction temperature ( q c) switching frequency (khz) -50 -25 0 25 50 75 100 125 150 480 485 490 495 500 505 510 515 520 d020 junction temperature ( q c) switching frequency (khz) -50 -25 0 25 50 75 100 125 150 1540 1550 1560 1570 1580 1590 1600 1610 1620 1630 1640 1650 1660 d021 junction temperature ( q c) pgood leakage current (na) -50 -25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 900 1000 1100 d017 ambient temperature ( q c) minimum on-time (ns) -50 -25 0 25 50 75 100 125 150 70 75 80 85 90 95 100 105 110 115 120 d018 i out = 0 a i out = 0.1 a i out = 0.5 a junction temperature ( q c) high-side peak current limit (a) -50 -25 0 25 50 75 100 125 150 11 11.5 12 12.5 13 13.5 14 14.5 15 d015 v in = 4.5 v v in = 12 v v in = 17 v junction temperature ( q c) pgood threshold ( of v ref ) -50 -25 0 25 50 75 100 125 150 86 88 90 92 94 96 98 100 102 104 106 108 110 d016 v (fb) falling (fault) v (fb) rising (good) v (fb) rising (fault) v (fb) falling (good)
10 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated typical characteristics (continued) figure 21. switching frequency vs rt/clk resistor (low range) figure 22. switching frequency vs rt/clk resistor (high range) r (rt/clk) (k : ) switching frequency (khz) 80 100 120 140 160 180 200 220 240 260 200 250 300 350 400 450 500 550 600 650 d023 r (rt/clk) (k : ) switching frequency (khz) 25 30 35 40 45 50 55 60 65 70 75 80 85 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 d024
11 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 7 detailed description 7.1 overview the tps54824 is a 17-v, 8-a, synchronous step-down (buck) converter with two integrated n-channel mosfets. to improve performance during line and load transients the device implements a constant frequency, peak current mode control which also simplifies external frequency compensation. the wide switching frequency of 200 khz to 1600 khz allows for efficiency and size optimization when selecting the output filter components. the switching frequency is adjusted using a resistor to ground on the rt/clk pin. the tps54824 also has an internal phase lock loop (pll) connected to the rt/clk pin that can be used to synchronize the switching cycle to the falling edge of an external system clock. the integrated mosfets allow for high efficiency power supply designs with continuous output currents up to 8 amperes. the mosfets have been sized to optimize efficiency for lower duty cycle applications. the device reduces the external component count by integrating a bootstrap recharge circuit. the bias voltage for the integrated high-side mosfet is supplied by a capacitor between the boot and sw pins. the boot capacitor voltage is monitored by a boot to sw uvlo (boot-sw uvlo) circuit allowing sw pin to be pulled low to recharge the boot capacitor. the device can operate at 100% duty cycle as long as the boot capacitor voltage is higher than the preset boot-sw uvlo threshold which is typically 2.2 v. the tps54824 has been designed for safe monotonic startup into pre-biased loads. the default start up is when vin is typically 4.1 v. the en pin has an internal pull-up current source that can be used to adjust the input voltage under voltage lockout (uvlo) with two external resistors. in addition, the internal pull-up current of the en pin allows the device to operate with the en pin floating. the operating current for the tps54824 is typically 580 a when not switching and under no load. when the device is disabled, the supply current is typically 3 a. the ss/trk (soft start/tracking) pin is used to minimize inrush currents or provide power supply sequencing during power up. a small value capacitor or resistor divider should be coupled to the pin for soft start or critical power supply sequencing requirements. the output voltage can be stepped down to as low as the 0.6 v voltage reference (v ref ). the device has a power good comparator (pgood) with hysteresis which monitors the output voltage through the fb pin. the pgood pin is an open drain mosfet which is pulled low when the fb pin voltage is less than 89% or greater than 108% of the reference voltage v ref and asserts high when the fb pin voltage is 91% to 106% of v ref . the device is protected from output overvoltage, overload and thermal fault conditions. the device minimizes excessive output overvoltage transients by taking advantage of the overvoltage circuit power good comparator. when the overvoltage comparator is activated, the high-side mosfet is turned off and prevented from turning on until the fb pin voltage is lower than 106% of the v ref . the device implements both high-side mosfet over current protection and bidirectional low-side mosfet over current protections which help control the inductor current and avoid current runaway. the device also shuts down if the junction temperature is higher than thermal shutdown trip point. the device is restarted under control of the soft start circuit automatically when the junction temperature drops 15 c typically below the thermal shutdown trip point.
12 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 7.2 functional block diagram 7.3 feature description 7.3.1 fixed frequency pwm control the device uses an adjustable fixed frequency, peak current mode control. the output voltage is compared through external resistors on the fb pin to an internal voltage reference by an error amplifier which drives the comp pin. an internal oscillator initiates the turn on of the high-side power switch. the error amplifier output is converted into a current reference which compares to the high-side power switch current. when the power switch current reaches current reference generated by the comp voltage level the high-side power switch is turned off and the low-side power switch is turned on. the device adds an internal slope compensation ramp to prevent subharmonic oscillations. the peak inductor current limit remains constant over the full duty cycle range. 7.3.2 continuous conduction mode operation (ccm) as a synchronous buck converter, the device works in ccm (continuous conduction mode) under all load conditions. error amplifier power stage & deadtime control logic boot charge uvlo current sense oscillator with pll slope compensation maximum clamp voltage reference overload recovery fb ss/trk comp rt/clk boot thermal shutdown en enable comparator shutdown logic shutdown enable threshold logic shutdown pgood ls mosfet current limit ov minimum clamp pulse skip i p i h vin uv current sense regulator vin boot uvlo sw pgnd hiccup shutdown hiccup shutdown hs mosfet current comparator agnd copyright ? 2016, texas instruments incorporated
13 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) 7.3.3 vin pins and vin uvlo the vin pin voltage supplies the internal control circuits of the device and provides the input voltage to the power converter system. the input voltage for vin can range from 4.5 v to 17 v. the device implements internal uvlo circuitry on the vin pin. the device is disabled when the vin pin voltage falls below the internal vin uvlo threshold. the internal vin uvlo threshold has a hysteresis of 200 mv. a voltage divider connected to the en pin can adjust the input voltage uvlo appropriately. see enable and adjustable uvlo for more details. 7.3.4 voltage reference and adjusting the output voltage the voltage reference system produces a precise 0.85%, 0.6 v voltage reference over temperature by scaling the output of a temperature stable band gap circuit. the output voltage is set with a resistor divider from the output (v out ) to the fb pin shown in figure 23 . it is recommended to use 1% tolerance or better divider resistors. start with a fixed value for the bottom resistor in the divider, typically 10 k , then use equation 1 to calculate the top resistor in the divider. to improve efficiency at light loads consider using larger value resistors. if the values are too high the regulator is more susceptible to noise and voltage errors from the fb input current are noticeable. the minimum output voltage and maximum output voltage can be limited by the minimum on time of the high side mosfet and bootstrap voltage (boot-sw voltage) respectively. figure 23. fb resistor divider (1) 7.3.5 error amplifier the device uses a transconductance error amplifier. the error amplifier compares the fb pin voltage to the lower of the ss/trk pin voltage or the internal 0.6-v voltage reference. the transconductance of the error amplifier is 1100 a/v. the frequency compensation network is connected between the comp pin and ground. when operating at current limit the comp pin voltage is clamped to a maximum level to improve response when the load current decreases. when fb is greater than the internal voltage reference or ss/trk the comp pin voltage is clamped to a minimum level and the devices enters a high-side skip mode. 7.3.6 enable and adjustable uvlo the en pin provides on/off control of the device. once the en pin voltage exceeds its threshold voltage, the device starts operation. if the en pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low operating current state. the en pin has an internal pull-up current source, ip, allowing the user to float the en pin for enabling the device. if an application requires controlling the en pin, an open drain or open collector output logic can be interfaced with the pin. out fbt fbb ref v r r 1 v u ? ? 1 tps54824 v out fb r fbt r fbb + 0.6 v copyright ? 2016, texas instruments incorporated
14 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) an external resistor divider can be added from vin to the en pin for adjustable uvlo and hysteresis as shown in figure 24 . the en pin has a small pull-up current ip which sets the default state of the pin to enable when no external components are connected. the pull-up current is also used to control the voltage hysteresis for the uvlo function since it increases by ih once the en pin crosses the enable threshold. the uvlo thresholds can be calculated using equation 2 and equation 3 . when using the adjustable uvlo function, 500 mv or greater hysteresis is recommended. figure 24. adjustable uvlo using en (2) vertical spacer (3) 7.3.7 soft start and tracking the tps54824 regulates to the ss/trk pin while its voltage is lower than the internal reference to implement soft start. a capacitor on the ss/trk pin to ground sets the soft start time. the ss/trk pin has an internal pull- up current source of 5 a that charges the external soft start capacitor. equation 4 calculates the required soft start capacitor value. the fb voltage will follow the ss/trk pin voltage with a 25 mv offset up to 90% of the internal voltage reference. when the ss/trk voltage is greater than 90% of the internal reference voltage the offset increases as the effective system reference transitions from the ss/trk voltage to the internal voltage reference. (4) if during normal operation, vin goes below the uvlo, en pin pulled below 1.15 v, or a thermal shutdown event occurs, the tps54824 stops switching and the ss/trk pin floats. when the vin goes above uvlo, en goes above 1.20 v, or a thermal shutdown is exited, the ss/trk pin is discharged to near ground before reinitiating a powering up sequence. ss ss ss ss ref i a t ms c nf 8.3 t ms v v u u ent enfalling enb stop enfalling ent p h r v r v v r i i u u enfalling start stop enrising ent enfalling p h enrising v v v v r v i 1 i v u ? ? 1 u ? ? 1 tps54824 vin en r ent r enb i h + i p copyright ? 2016, texas instruments incorporated
15 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) when the comp pin voltage is clamped by the maximum comp clamp in an overload condition the ss/trk pin is discharged to near the fb voltage. when the overload condition is removed, the soft-start circuit controls the recovery from the fault output level to the nominal output regulation voltage. at the beginning of recovery a spike in the output voltage may occur while the comp voltage transitions from the maximum clamp to the value determined by the loop. 7.3.8 safe start-up into pre-biased outputs the device has been designed to prevent the low-side mosfet from discharging a pre-biased output. during monotonic pre-biased startup, the low-side mosfet is not allowed to sink current until the ss/trk pin voltage is higher than the fb pin voltage and the high-side mosfet begins to switch. the one exception is if the boot- sw voltage is below the uvlo threshold. while in boot-sw uvlo, the low-side mosfet is allowed to turn on to charge the boot capacitor. the low-side mosfet reverse current protection provides another layer of protection for the device after the high-side mosfet begins to switch. 7.3.9 power good the pgood pin is an open-drain output requiring an external pull-up resistor to output a high signal. once the fb pin is between 91% and 106% of the internal voltage reference and ss/trk is greater than 0.75 v, after a 272 cycle deglitch time the pgood pin is de-asserted and the pin floats. a pull-up resistor between the values of 10 k ? and 100 k ? to a voltage source that is 6.5 v or less is recommended. pgood is in a defined state once the vin input voltage is greater than 1 v but with reduced current sinking capability. when the fb is lower than 89% or greater than 108% of the nominal internal reference voltage, after a 16 cycle deglitch time the pgood pin is pulled low. pgood is immediately pulled low if vin falls below its uvlo, en pin is pulled low or the tps54824 enters thermal shutdown.
16 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) 7.3.10 sequencing (ss/trk) many of the common power supply sequencing methods can be implemented using the ss/trk, en and pgood pins. the sequential method is illustrated in figure 25 using two tps54824 or similar devices. the power good of the first device is coupled to the en pin of the second device which enables the second power supply once the primary supply reaches regulation. figure 26 shows the method implementing ratiometric sequencing by connecting the ss/trk pins of two devices together. the regulator outputs ramp up and reach regulation at the same time. when calculating the soft-start time the current source must be doubled in equation 4 . figure 25. sequential start-up sequence figure 26. ratiometric start-up sequence en tps54824 ss/trk pgood en tps54824 ss/trk pgood copyright ? 2016, texas instruments incorporated en tps54824 ss/trk pgood en tps54824 ss/trk pgood copyright ? 2016, texas instruments incorporated
17 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) ratiometric and simultaneous power supply sequencing can be implemented by connecting the resistor network of r trt and r trb shown in figure 27 to the output of the power supply that needs to be tracked or another voltage reference source. using equation 6 and equation 7 , the tracking resistors can be calculated to initiate the v out2 slightly before, after or at the same time as v out1 . equation 5 is the voltage difference between v out1 and v out2 . to design a ratiometric start-up in which the v out2 voltage is slightly greater than the v out1 voltage when v out2 reaches regulation, use a negative number in equation 6 and equation 7 for deltav. equation 5 results in a positive number for applications where the v out2 is slightly lower than v out1 when v out2 regulation is achieved. the deltav variable is zero volts for simultaneous sequencing. to minimize the effect of the inherent ss/trk to fb offset (vssoffset = 25 mv) in the soft-start circuit and the offset created by the pull-up current source (iss = 5 a) and tracking resistors, the vssoffset and iss are included as variables in the equations. to ensure proper operation of the device, the calculated r trt value from equation 6 must be greater than the value calculated in equation 8 . (5) vertical spacer (6) vertical spacer (7) vertical spacer (8) figure 27. ratiometric and simultaneous start-up sequence out2 trt ref v v vssoffset r v iss ' u out1 out2 v v v ' en tps54824 ss/trk pgood en tps54824 ss/trk pgood r trt r trb r fbb r fbt v out1 v out2 copyright ? 2016, texas instruments incorporated trt out1 r 2800 v 180 v ! u u ' ref trt trb out2 ref v r r v v v u '
18 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) 7.3.11 adjustable switching frequency (rt mode) in rt mode, a resistor (rt resistor) is connected between the rt/clk pin and agnd. the switching frequency of the device is adjustable from 200 khz to 1600 khz by placing a maximum of 250 k and minimum of 30.1 k ? respectively. to determine the rt resistance for a given switching frequency, use equation 9 . to reduce the solution size one would set the switching frequency as high as possible, but tradeoffs of the supply efficiency and minimum controllable on-time should be considered. equation 10 can be used to calculate the switching frequency for a given rt resistance. (9) vertical spacer (10) 7.3.12 synchronization (clk mode) an internal phase locked loop (pll) has been implemented to allow synchronization from 200 khz to 1600 khz, and to easily switch from rt mode to clk mode. to implement the synchronization feature, connect a square wave clock signal to the rt/clk pin with a duty cycle from 20% to 80%. the clock signal amplitude must transition lower than 0.8 v and higher than 2 v. the start of the switching cycle is synchronized to the falling edge of the rt/clk pin. in applications where both rt mode and clk mode are needed, the device can be configured as shown in figure 28 . before the external clock is present, the device works in rt mode and the switching frequency is set by rt resistor. when the external clock is present, the clk mode overrides the rt mode. the first time the sync pin is pulled above the rt/clk high threshold (2 v), the device switches from the rt mode to the clk mode and the rt/clk pin becomes high impedance as the pll starts to lock onto the frequency of the external clock. if the input clock goes away the internal clock frequency begins to drop and after 10 s without a clock the device returns to rt mode. output undershoot while the switching frequency drops can occur. output overshoot can also occur when the switching frequency steps back up to the rt mode frequency. a high impedance tri- state buffer as shown in figure 30 is recommended for best performance during the transition from clk mode to rt mode because it minimizes the loading on the rt/clk pin allowing faster transition back to rt mode. figure 31 shows the typical performance for the transition from rt mode to clk mode then back to rt mode. a series rc circuit as shown in figure 29 can also be used to interface the rt/clk pin but the capacitive load slows down the transition back to rt mode. the series rc circuit is not recommended if the transition from clk mode to rt mode is important. figure 28. simplified circuit when using both rt mode and clk mode figure 29. interfacing to the rt/clk pin with series rc rt/clk r t rt/clk mode select tps54824 copyright ? 2016, texas instruments incorporated rt/clk r t 47 pf 2 k tps54824 copyright ? 2016, texas instruments incorporated 0.973 sw f khz 43660 rt k u : 1.028 sw rt k 58650 f khz : u
19 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 30. interfacing to the rt/clk pin with buffer figure 31. rt to clk to rt transition with buffer 7.3.13 bootstrap voltage and 100% duty cycle operation (boot) the device provides an integrated bootstrap voltage regulator. a small capacitor between the boot and sw pins provides the gate drive voltage for the high side mosfet. the boot capacitor is refreshed when the low- side mosfet is on. the recommended value of the boot capacitor is 0.1 f. a ceramic capacitor with an x7r or x5r grade dielectric with a voltage rating of 10 v or higher is recommended for stable performance over temperature and voltage. when operating with a low voltage difference from input to output, the high side mosfet of the device will operate at 100% duty cycle as long as the boot to sw pin voltage is greater than 2.2 v. the device will begin to transition to 100% duty cycle operation when the high-side mosfet off-time is less than 100 ns typical. when the voltage from boot to sw drops below 2.2 v, the high-side mosfet is turned off due to boot uvlo and the low side mosfet pulls sw low to recharge the boot capacitor. when operating at 100% duty cycle the high-side mosfet can remain on for many switching cycles before the mosfet is turned off to refresh the capacitor because the gate drive current sourced by the boot capacitor is small. the effective switching frequency reduced and the effective maximum duty cycle of the switching regulator is near 100%. the output voltage of the converter during dropout is mainly influenced by the voltage drops across the power mosfet, the inductor resistance, and the printed circuit board resistance. 7.3.14 output overvoltage protection (ovp) the tps54824 incorporates an output overvoltage protection (ovp) circuit to minimize output voltage overshoot. the ovp feature minimizes the overshoot by comparing the fb pin voltage to the ovp threshold. the ovp threshold is the same as the 108% pgood threshold. if the fb pin voltage is greater than the ovp threshold the high-side mosfet is turned off preventing current from flowing to the output and minimizing output overshoot. when the high-side mosfet turns off, the low-side mosfet turns on and the current in the inductor discharges. the output voltage can overshoot the ovp threshold as the current in the inductor discharges to 0 a. when the fb voltage drops lower than the 106% pgood threshold, the high-side mosfet is allowed to turn on at the next clock cycle. 7.3.15 overcurrent protection the device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side mosfet and the low-side mosfet. in an extended overcurrent condition the device will enter hiccup to reduce power dissipation. ch3: rt/clk ch2: vout dc offset ch1: sw v in = 12 v, i out = 4 a, v out = 3.3 v, fsw = 1.2 mhz rt/clk r t oe tps54824 copyright ? 2016, texas instruments incorporated
20 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) 7.3.15.1 high-side mosfet overcurrent protection the device implements current mode control which uses the comp pin voltage to control the turnoff of the high- side mosfet and the turnon of the low-side mosfet on a cycle-by-cycle basis. each cycle the switch current and the current reference generated by the comp pin voltage are compared, when the peak switch current intersects the current reference the high-side switch is turned off. the maximum peak switch current through the high-side mosfet for overcurrent protection is done by limiting the current reference internally. if the peak current required to regulate the output is greater than the internal limit, the output voltage is pulled low and the error amplifier responds by driving the comp pin high. the maximum comp voltage is then clamped by an internal comp clamp circuit. if the comp voltage is clamped high for more than the hiccup wait time of 512 switching cycles, the device will shut down itself and restart after the hiccup time of 16384 cycles. 7.3.15.2 low-side mosfet overcurrent protection while the low-side mosfet is turned on the current through it is monitored. during normal operation the low- side mosfet sources current to the load. at the end of every clock cycle, the low-side mosfet sourcing current is compared to the internally set low-side sourcing current limit. if the low-side sourcing current is exceeded the high-side mosfet is not turned on and the low-side mosfet stays on for the next cycle. the high-side mosfet is turned on again when the low-side current is below the low-side sourcing current limit at the start of a cycle. the low-side sourcing current limit prevents current runaway. the low-side mosfet may also sink current from the load. if the low-side sinking current limit is exceeded the low-side mosfet is turned off immediately for the rest of that clock cycle. in this scenario both mosfets are off until the start of the next cycle. if the low-side mosfet turns off due to sinking current limit protection, the low-side mosfet can only turn on again after the high-side mosfet turns on then off or if the device enters boot uvlo. 7.4 device functional modes the en pin and a vin uvlo is used to control turn on and turn off of the tps54824. the device becomes active when v (vin) exceeds the 4.1 v typical uvlo and when v (en) exceeds 1.20 v typical. the en pin has an internal current source to enable the output when the en pin is left floating. if the en pin is pulled low the device is put into a low quiescent current state.
21 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 8 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 8.1 application information the tps54824 is a synchronous buck converter designed for 4.5 v to 17 v input and 8 a load. this procedure illustrates the design of a high-frequency switching regulator using ceramic output capacitors. alternatively the webench ? software can be used to generate a complete design. the webench ? software uses an interactive design procedure and accesses a comprehensive database of components when generating a design. this section presents a simplified discussion of the design process. 8.2 typical application figure 32. tps54824 4.5-v to 15-v input, 1.8-v output converter application schematic 8.2.1 design requirements for this design example, use the parameters shown in table 1 . table 1. design parameters parameter example value input voltage range (v in ) 4.5 to 15 v, 12 v nominal output voltage (v out ) 1.8 v transient response +/- 4%, +/- 72 mv output ripple voltage 0.5%, 9 mv output current rating (i out ) 8 a operating frequency (f sw ) 700 khz copyright ? 2016, texas instruments incorporated
22 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.2 detailed design procedure 8.2.2.1 switching frequency the first step is to decide on a switching frequency for the converter. it is capable of running from 200 khz to 1.6 mhz. typically the highest switching frequency possible is desired because it will produce the smallest solution size. a high switching frequency allows for lower valued inductors and smaller output capacitors compared to a power supply that switches at a lower frequency. the main trade off made with selecting a higher switching frequency is extra switching power loss, which hurt the converter ? s efficiency. the maximum switching frequency for a given application is limited by the minimum on-time of the converter and is estimated with equation 11 . using a maximum minimum on-time of 150 ns for the tps54824 and 15 v maximum input voltage for this application, the maximum switching frequency is 800 khz. considering the 10% tolerance of the switching frequency, a switching frequency of 700 khz was selected. equation 12 calculates r7 to be 69.7 k . a standard 1% 69.8 k value was chosen in the design. (11) vertical spacer (12) 8.2.2.2 output inductor selection to calculate the value of the output inductor, use equation 13 . k ind is a ratio that represents the amount of inductor ripple current relative to the maximum output current. the inductor ripple current is filtered by the output capacitor. therefore, choosing high inductor ripple currents impacts the selection of the output capacitor since the output capacitor must have a ripple current rating equal to or greater than the inductor ripple current. additionally with current mode control the sensed inductor current ripple is used in the pwm modulator. choosing small inductor ripple currents can degrade the transient response performance or introduce jitter in the duty cycle. the inductor ripple, k ind is normally from 0.2 to 0.4 for the majority of applications giving a peak to peak ripple current range of 1.6 a to 3.2 a. for applications requiring operation near the minimum on-time, with on-times less than 200 ns, the target iripple must be 2.4 a or larger. for other applications the target iripple should be 0.8 a or larger. for this design example, k ind = 0.3 is used and the inductor value is calculated to be 0.94 h. the next standard value 1 h is selected. it is important that the rms current and saturation current ratings of the inductor not be exceeded. the rms and peak inductor current can be found from equation 15 and equation 16 . for this design, the rms inductor current is 8.0 a and the peak inductor current is 9.1 a. the chosen inductor is a cyntec cmle063t-1r0ms. it has a saturation current rating of 16.0 a (30% inductance loss) and a rms current rating of 16.0 a (40 c temperature rise). the dc series resistance is 5.6 m typical. the current flowing through the inductor is the inductor ripple current plus the output current. during power up, faults or transient load conditions, the inductor current can increase above the calculated peak inductor current level calculated in equation 16 . in transient conditions, the inductor current can increase up to the switch current limit of the device. for this reason, the most conservative approach is to specify the ratings of the inductor based on the switch current limit rather than the steady-state peak inductor current. (13) vertical spacer (14) vertical spacer (15) vertical spacer - | vinmax vout vout l1 = io kind vinmax sw out sw in v 1 f max tonmin v max u 1.028 sw rt k 58650 f khz : u ? ? - ? | ? 2 2 1 vo (vinmax vo) ilrms = io + 12 vinmax l1 sw - | vinmax vout vout iripple = l1 vinmax sw
23 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated (16) 8.2.2.3 output capacitor there are two primary considerations for selecting the value of the output capacitor. the output voltage ripple and how the regulator responds to a large change in load current. the output capacitance needs to be selected based on the more stringent of these two criteria. the desired response to a large change in the load current is the first criteria and is typically the most stringent. the output capacitor supplies or absorbs charge until the regulator responds to the load step. the regulator does not respond immediately to a large, fast increase or decrease in load current. a regulator usually needs two or more clock cycles for the control loop to sense the change in output voltage then adjust the peak switch current in response to the change in load. as an estimation, the output capacitance must be large enough to supply the difference in current for 2 clock cycles to maintain the output voltage within the specified range. at higher switching frequencies the fastest response time is limited to about 2 s. equation 17 shows the minimum output capacitance necessary, where i out is the change in output current, tresponse is the regulator's estimated response time and v out is the allowable change in the output voltage. the maximum of 2/fsw or 2 s should be used for the response time in the output capacitance calculation. the response to a transient load also depends on the loop compensation and slew rate of the transient load. this calculation assumes the loop compensation is designed for the output filter with the equations later on in this procedure. for this example, the transient load response is specified as a 4% change in v out for a load step of 4 a. therefore, i out is 4 a and v out is 72 mv. using these numbers with a 2.9 s response time gives a target capacitance of 159 f. this value does not take the esr of the output capacitor into account in the output voltage change. for ceramic capacitors, the effect of the esr can be small enough to be ignored. aluminum electrolytic and tantalum capacitors have higher esr that must be considered for load step response. equation 18 calculates the minimum output capacitance needed to meet the output voltage ripple specification. where fsw is the switching frequency, vripple is the maximum allowable output voltage ripple, and iripple is the inductor ripple current. in this case, the target maximum output voltage ripple is 9 mv. under this requirement, equation 18 yields 46 f. vertical spacer (17) vertical spacer (18) where: ? i out is the change in output current ? v out is the allowable change in the output voltage ? f sw is the regulators switching frequency vertical spacer equation 19 calculates the maximum combined esr the output capacitors can have to meet the output voltage ripple specification and this shows the esr should be less than 4 m ? . in this case ceramic capacitors will be used and the combined esr of the ceramic capacitors in parallel is much less than 4 m ? . capacitors also have limits to the amount of ripple current they can handle without producing excess heat and failing. an output capacitor that can support the inductor ripple current must be specified. capacitor datasheets specify the rms (root mean square) value of the maximum ripple current. equation 20 can be used to calculate the rms ripple current the output capacitor needs to support. for this application, equation 20 yields 660 ma and the ceramic capacitors used in this design will have a ripple current rating much higher than this. (19) vertical spacer voripple resr < iripple 1 1 co > voripple 8 sw iripple | response iout co t vout ' ! u ' iripple ilpeak = iout + 2
24 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated (20) x5r and x7r ceramic dielectrics or similar should be selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. the output capacitor must also be selected with the dc bias and ac voltage derating taken into account. the derated capacitance value of a ceramic capacitor due to dc voltage bias and ac rms voltage is usually found on the manufacturer's website. for this application example, four 47 f 6.3 v 1206 x5r ceramic capacitors each with 3 m ? of esr are used. the estimated capacitance after derating using the capacitor manufacturer's website is 29 f each. with 4 parallel capacitors the total output capacitance is 116 f and the esr is 0.7 m . the effective capacitance used is less than originally calculated above because testing the real circuit on the bench showed that less capacitance was required to achieve the desired response. 8.2.2.4 input capacitor the tps54824 requires input decoupling ceramic capacitors type x5r, x7r or similar from vin to pgnd placed as close as possible to the ic. at least 4.7 f of effective capacitance is required and some applications may require a bulk capacitance. a 0.1 f capacitor must be placed by both vin pins 2 and 11 to provide high frequency bypass to reduce overshoot and ringing on vin and sw. the additional bypass capacitance can be placed near either pin. the effective capacitance must include any dc voltage bias and ac voltage effects. the voltage rating of the input capacitor must be greater than the maximum input voltage. the capacitor must also have a ripple current rating greater than the maximum rms input current of the tps54824. the rms input current can be calculated using equation 21 . for this example design, a ceramic capacitor with at least a 25 v voltage rating is required to support the maximum input voltage. two 10 f 1206 x5r 35 v and two 0.1 f 0603 x7r 25 v capacitors in parallel has been selected to be placed on both sides of the ic near both vin pins to pgnd pins. based on the capacitor manufacturer's website, the total ceramic input capacitance derates to 5.6 f at the nominal input voltage of 12 v. a 100 f bulk capacitance is also used in this circuit to bypass long leads when connected a lab bench top power supply. the input capacitance value determines the input ripple voltage of the regulator. the input voltage ripple can be calculated using equation 22 . the maximum input ripple occurs when operating nearest to 50% duty cycle. using the nominal design example values of ioutmax = 8 a, cin = 5.6 f, and f sw = 700 khz, the input voltage ripple with the 12 v nominal input is 260 mv and the rms input ripple current with the 4.5 v minimum input is 3.0 a. (21) vertical spacer (22) 8.2.2.5 output voltage resistors selection the output voltage is set with a resistor divider created by r8 (r fbt ) and r6 (r fbb ) from the output node to the fb pin. it is recommended to use 1% tolerance or better resistors. for this example design, 6.04 k was selected for r8. using equation 23 , r6 is calculated as 12.08 k . the nearest standard 1% resistor is 12.1 k . (23) out fbt fbb ref v r r 1 v u ? ? 1 sw vout vout iout max 1 vin vin vin cin f u u ? ? 1 ' u ( ) vinmin vout vout icirms = iout vinmin vinmin - - | vout (vinm ax vout) icorm s = 12 vinm ax l1 sw
25 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.2.6 soft-start capacitor selection the soft-start capacitor determines the amount of time it takes for the output voltage to reach its nominal programmed value during power up. this is useful if a load requires a controlled voltage slew rate. this is also used if the output capacitance is very large and would require large amounts of current to quickly charge the capacitor to the output voltage level. the large currents necessary to charge the capacitor may make the tps54824 reach its current limit or cause the input voltage rail to sag due excessive current draw from the input power supply. limiting the output voltage slew rate solves both of these problems. the soft-start capacitor value can be calculated using equation 24 . for the example circuit, the soft-start time is not too critical since the output capacitor value is 4 x 47 f which does not require much current to charge to 1.8 v. the example circuit has the soft-start time set to an arbitrary value of 1 ms which requires a 8.2-nf capacitor. (24) 8.2.2.7 undervoltage lockout set point the undervoltage lockout (uvlo) is adjusted using the external voltage divider network of r2 (r ent ) and r9 (r enb ). the uvlo has two thresholds; one for power up when the input voltage is rising and one for power-down or brown outs when the input voltage is falling. for the example design, the supply should turn on and start switching once the input voltage increases above 4.5 v (uvlo start or enable). after the regulator starts switching, it should continue to do so until the input voltage falls below 4.0 v (uvlo stop or disable). equation 2 and equation 3 can be used to calculate the values for the upper and lower resistor values. for the voltages specified, the standard resistor value used for r2 is 86.6 k ? and for r4 is 30.9 k ? . 8.2.2.8 bootstrap capacitor selection a 0.1- f ceramic capacitor must be connected between the boot to sw pin for proper operation. a 1 to 5.6 resistor can be added in series with the boot capacitor to slow down the turn on of the high-side mosfet. this can reduce voltage spikes on the sw node with the trade off of more power loss and lower efficiency. 8.2.2.9 pgood pull-up resistor a 100 k resistor is used to pull-up the power good signal when fb conditions are met. the pull-up voltage source must be less than the 6.5 v absolute maximum of the pgood pin. 8.2.2.10 compensation there are several methods used to compensate dc - dc regulators. the method presented here is easy to calculate and ignores the effects of the slope compensation internal to the device. because the slope compensation is ignored, the actual cross-over frequency will usually be lower than the cross-over frequency used in the calculations. this method assumes the cross-over frequency is between the modulator pole and the esr zero and the esr zero is at least 10 times greater the modulator pole. this is the case when using low esr output capacitors. use the webench ? software for more accurate loop compensation. these tools include a more comprehensive model of the control loop. to get started, the modulator pole, fpmod, and the esr zero, fz1 must be calculated using equation 25 and equation 26 . for cout, use a derated value of 116 f and an esr of 1 m . use equations equation 27 and equation 28 , to estimate a starting point for the crossover frequency, fco, to design the compensation. for the example design, fpmod is 6.1 khz and fzmod is 1370 khz. equation 27 is the geometric mean of the modulator pole and the esr zero. equation 28 is the mean of modulator pole and one half the switching frequency. equation 27 yields 92 khz and equation 28 gives 46 khz. use the lower value of equation 27 or equation 28 for an initial crossover frequency. next, the compensation components are calculated. a resistor in series with a capacitor is used to create a compensating zero. a capacitor in parallel to these two components forms the compensating pole. (25) vertical spacer (26) ss ss ss ss ref i a t ms c nf 8.3 t ms v v u u 1 z mod = 2 resr cout | p ioutmax p mod = 2 vout cout | p
26 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated vertical spacer (27) vertical spacer (28) to determine the compensation resistor, r5, use equation 29 . r5 is calculated to be 5.71 k ? and the closest standard value 5.76 k . use equation 30 to set the compensation zero to the modulator pole frequency. equation 30 yields 4500 pf for compensating capacitor c18 and the closest standard value is 4700 pf. (29) where: ? power stage transconductance, gm ps = 16 a/v ? v out = 1.8 v ? v ref = 0.6 v ? error amplifier transconductance, gm ea = 1100 a/v (30) a compensation pole is implemented using an additional capacitor c17 in parallel with the series combination of r5 and c18. this capacitor is recommended to help filter any noise that may couple to the comp voltage signal. use the larger value of equation 31 and equation 32 to calculate the c17 and to set the compensation pole. c17 is calculated to be the largest of 20 pf and 79 pf. the closest standard value is 82 pf. (31) vertical spacer (32) this design example uses type iii compensation by adding the feed forward capacitor c19 in parallel with the upper feedback resistor. the use of this capacitor for type iii compensation is optional. type iii compensation increases the crossover and adds phase boost above what is possible from type ii compensation because it places an additional zero/pole pair. this zero/pole pair is not independent. as a result once the zero location is chosen, the pole is fixed as well. the zero is placed 1.5 times above the intended crossover frequency by calculating the value of c19 with equation 33 . the calculated value is 190 pf and the closest standard value is 180 pf. (33) the initial compensation based on these calculations is r5 = 5.76 k , c18 = 4700 pf, c17 = 82 pf and c19 = 180 pf. these values yield a stable design but after testing the real circuit these values were changed to target a higher crossover frequency to improve transient response performance. the crossover frequency is increased by increasing the value of r5 and decreasing the value of all 3 compensation capacitors. the final values used in this example are r5 = 9.53 k , c18 = 2200 pf, c17 = 27 pf and c19 = 100 pf. u s u u ff fbt co 1 c 3 r f hf comp sw 1 c r f s u u out esr hf comp c r c r u comp comp pmod 1 c 2 r f u s u u co out out comp ps ref ea 2 f c v r gm v gm u s u u u ? ? u ? 1 ? 1 2 sw p f f f = co mod p z f f f = co mod mod
27 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 8.2.3 application curves t j = 25 c v out = 1.8 v f sw = 700 khz figure 33. efficiency t j = 25 c v out = 1.8 v f sw = 700 khz figure 34. efficiency (log scale) t j = 25 c v out = 1.8 v f sw = 700 khz figure 35. load regulation t j = 25 c v out = 1.8 v f sw = 700 khz figure 36. line regulation v in = 12 v v out = 1.8 v i out = 4 a figure 37. loop response v in = 12 v v out = 1.8 v figure 38. transient response output current (a) efficiency (%) 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1 0 10 20 30 40 50 60 70 80 90 100 d026 v in = 5 v v in = 12 v output current (a) load regulation (%) phase (degree) 100 200 500 1000 10000 100000 1000000 -40 -120 -30 -90 -20 -60 -10 -30 0 0 10 30 20 60 30 90 40 120 50 150 60 180 70 210 80 240 d029 gain phase output current (a) load regulation (%) 0 1 2 3 4 5 6 7 8 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 d027 v in = 5 v v in = 12 v output current (a) line regulation (%) 4 5 6 7 8 9 10 11 12 13 14 15 16 17 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 d028 i out = 0 a i out = 4 a i out = 8 a output current (a) efficiency (%) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 50 55 60 65 70 75 80 85 90 95 100 d025 v in = 5 v v in = 12 v
28 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated v in = 12 v v out = 1.8 v i out = 0 a figure 39. output ripple, no load v in = 12 v v out = 1.8 v i out = 8 a figure 40. output ripple, full load v in = 12 v v out = 1.8 v i out = 0 a figure 41. input voltage ripple, no load v in = 12 v v out = 1.8 v i out = 8 a figure 42. input voltage ripple, full load r load = 1 figure 43. v in startup r load = 1 figure 44. en startup
29 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated r load = 1 v in = 12 v figure 45. v in shutdown r load = 1 figure 46. en shutdown v in = 12 v figure 47. en startup with pre-biased output v in = 12 v i out = short figure 48. output short circuit response v in = 12 v i out = short figure 49. hiccup mode current limit v in = 12 v i out = short removed figure 50. hiccup mode recovery
30 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 9 power supply recommendations the tps54824 is designed to be powered by a well regulated dc voltage between 4.5 and 17 v. the tps54824 is a buck converter so the input supply voltage must be greater than the desired output voltage to regulate the output voltage to the desired value. if the input supply voltage is not high enough the output voltage will begin to drop. input supply current must be appropriate for the desired output current. 10 layout 10.1 layout guidelines ? vin and pgnd traces should be as wide as possible to reduce trace impedance and improve heat dissipation. ? an input capacitor is required on both vin pins of the ic and must be placed as close as possible to the ic. ? the pgnd trace between the output capacitor and the pgnd pin should be as wide as possible to minimize its trace impedance. ? provide sufficient vias for the input capacitor and output capacitor. ? keep the sw trace as physically short and wide as practical to minimize radiated emissions. ? a separate vout path should be connected to the upper feedback resistor. ? voltage feedback loop should be placed away from the high-voltage switching trace. it is preferable to use ground copper near it as a shield. ? the trace connected to the fb node should be as small as possible to avoid noise coupling. ? place components connected to the rt/clk, fb, comp and ss/trk pins as close to the ic as possible and minimize traces connected to these pins to avoid noise coupling. ? agnd must be connected to pgnd on the pcb. connect agnd to pgnd in a region away from switching currents. 10.2 layout example figure 51 through figure 54 shows an example pcb layout and the following list provides a description of each layer. ? the top layer has all components and the main traces for vin, sw, vout and pgnd. both vin pins are bypassed with two input capacitors placed as close as possible to the ic. multiple vias are placed near the input and output capacitors. the agnd trace is connected to pgnd with a wide trace away from the input capacitors to minimize switching noise. ? midlayer 1 is used to route the boot pin to the boot-sw capacitor (cbt). the rest of this layer is covered with pgnd. ? midlayer 2 has a wide trace connecting both vin pins of the ic. it also has a parallel trace for vout to minimize trace resistance. the rest of this layer is covered with pgnd. ? the bottom layer has the trace connecting the fb resistor divider to vout at the point of regulation. pgnd is filled into the rest of this layer to aid with thermal performance.
31 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated layout example (continued) figure 51. tps54824 layout top figure 52. tps54824 layout midlayer 1 figure 53. tps54824 layout midlayer 2 figure 54. tps54824 layout bottom
32 tps54824 slvsdc9 ? november 2016 www.ti.com product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 10.3 alternate layout example figure 55 through figure 58 shows an alternate example pcb layout with unsymmetrical placement of the input capacitors and output capacitors. both vin pins are still bypassed with an input capacitor placed as close as possible to the ic. figure 55. tps54824 alternate layout top figure 56. tps54824 alternate layout midlayer 1 figure 57. tps54824 alternate layout midlayer 2 figure 58. tps54824 alternate layout bottom
33 tps54824 www.ti.com slvsdc9 ? november 2016 product folder links: tps54824 submit documentation feedback copyright ? 2016, texas instruments incorporated 11 device and documentation support 11.1 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 11.2 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 11.3 trademarks hotrod, e2e are trademarks of texas instruments. webench is a registered trademark of texas instruments. 11.4 electrostatic discharge caution these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 11.5 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 12 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 1-dec-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples TPS54824RNVR active vqfn-hr rnv 18 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 54824 tps54824rnvt active vqfn-hr rnv 18 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year -40 to 150 54824 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 1-dec-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS54824RNVR vqfn- hr rnv 18 3000 330.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 tps54824rnvt vqfn- hr rnv 18 250 180.0 12.4 3.75 3.75 1.15 8.0 12.0 q1 package materials information www.ti.com 29-nov-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) TPS54824RNVR vqfn-hr rnv 18 3000 367.0 367.0 35.0 tps54824rnvt vqfn-hr rnv 18 250 210.0 185.0 35.0 package materials information www.ti.com 29-nov-2016 pack materials-page 2
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